class Rouge::Lexers::VHDL

def self.keywords
  @keywords ||= Set.new %w(
  access after alias all architecture array assert assume assume_guarantee attribute
  begin block body buffer bus case component configuration constant context cover
  default disconnect downto else elsif end entity exit fairness file for force function
  generate generic group guarded if impure in inertial inout is label library linkage
  literal loop map new next null of on open others out package parameter port postponed
  procedure process property protected pure range record register reject release report
  return select sequence severity shared signal strong subtype then to transport type
  unaffected units until use variable vmode vprop vunit wait when while with
  )
end

def self.keywords_type
  @keywords_type ||= Set.new %w(
  bit bit_vector boolean boolean_vector character integer integer_vector natural positive
  real real_vector severity_level signed std_logic std_logic_vector std_ulogic
  std_ulogic_vector string unsigned time time_vector
  )
end

def self.operator_words
  @operator_words ||= Set.new %w(
  abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
  )
end